VQ4SNN technique cuts FPGA memory use 61% for spiking neural networks

Spiking Neural Networks (SNNs) promise energy-efficient inference for edge AI, but deploying them on FPGAs is hampered by limited on-chip memory for synaptic weights. A new paper from Dimitrios Sekertzis and Giorgos Dimitrakopoulos introduces VQ4SNN, a hardware-aware architecture that applies vector quantization (VQ) to dramatically reduce memory footprint. VQ4SNN organizes weight storage into a two-level hierarchy: compact pointers reference a shared codebook of quantized weight vectors, eliminating the need to store each weight independently. The design integrates FPGA-aware memory mapping with analytical VQ parameter selection, ensuring efficient deployment without sacrificing accuracy. Experimental results show a 52–61% reduction in block RAM (BRAM) usage compared to state-of-the-art uncompressed FPGA SNN accelerators, with no increase in overall logic utilization.

This work marks the first application of vector quantization to pipelined spatial-dataflow SNN accelerators on FPGAs, targeting a key bottleneck in edge AI hardware. By enabling dense SNN models to fit on smaller, cheaper FPGAs, VQ4SNN broadens the feasibility of low-power, real-time inference for applications like sensor processing, robotics, and IoT. The technique maintains inference accuracy while slashing memory demands, suggesting a viable path for scaling SNN deployment on resource-constrained devices. As edge AI continues to push toward energy-efficient architectures, memory compression methods like VQ4SNN will be critical for bringing biologically-inspired neural networks out of the lab and into production.