VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Researchers' new AI system generates synthesizable Verilog for large hardware designs with minimal human intervention.
A team of researchers led by Sazzadul Islam has introduced VeriGraphi, a novel multi-agent framework designed to tackle one of hardware design's most persistent challenges: automatically generating synthesizable Register Transfer Level (RTL) code for large, complex systems. Current large language models (LLMs) struggle with this task, often losing context across modules, hallucinating interfaces, and failing to maintain structural coherence as design complexity grows, especially when specifications include informal prose, figures, and tables.
VeriGraphi's core innovation is its use of a spec-anchored Knowledge Graph (KG) as the architectural foundation for its generation pipeline. This framework first constructs a Hardware Design Abstraction (HDA), a structured graph that explicitly encodes the module hierarchy, port-level interfaces, wiring semantics, and inter-module dependencies. This graph is built through iterative, multi-agent analysis of the specification document, creating a deterministic, machine-checkable scaffold *before* any code is written. Guided by this KG, a progressive coding module then incrementally generates pseudo-code and finally, synthesizable Verilog RTL, enforcing interface consistency and dependency correctness at every submodule stage.
The system was rigorously evaluated on a benchmark of three representative specification documents from the National Institute of Standards and Technology (NIST), alongside their corresponding implementations. A detailed case study on generating a RV32I RISC-V processor illustrated the full pipeline's capabilities. The results demonstrate that VeriGraphi enables reliable, hierarchical RTL generation with minimal human intervention, marking a significant step forward for AI-assisted hardware design. This approach directly addresses the shortcomings of raw LLMs by providing a structured reasoning process that mirrors expert human design, ensuring the final output maintains strong functional correctness.
- Uses a spec-anchored Knowledge Graph to encode hardware design structure before code generation, preventing LLM hallucinations.
- Multi-agent system iteratively analyzes specifications to build a deterministic scaffold of modules, interfaces, and dependencies.
- Successfully generated a functional RV32I RISC-V processor from specs, tested on NIST benchmarks with minimal human input.
Why It Matters
Automates the translation of complex hardware specifications into working RTL code, drastically accelerating chip design and verification cycles.