UniSpike slashes neuromorphic chip traffic by half with smarter packet design

Neuromorphic chips accelerate spiking neural networks (SNNs) by emulating biological neurons, but their packet-switched communication fabric suffers from repeated address transmissions—each spike carries a full destination address even when many spikes head to the same core. The overhead is severe: in representative SNN workloads, duplicate address transmissions account for up to 49% of the total traffic. UniSpike, a new hardware-software co-design from Zhejiang University, addresses this by bundling multiple spikes destined for the same core into a single compact packet.

The system combines three innovations: destination-centric spike scheduling that accumulates spikes before sending, lightweight runtime packet assembly hardware integrated into the router, and a destination-aware SNN partitioning algorithm that groups neurons by their target core. Across diverse benchmarks, UniSpike reduces on-chip traffic by 1.93× on average, yielding a 1.77× speedup and 1.50× energy efficiency improvement over prior art. Accepted at the 63rd Design Automation Conference (DAC 2026), UniSpike shows that eliminating address redundancy is a key lever for scaling neuromorphic systems.