UCAgent: An End-to-End Agent for Block-Level Functional Verification

A team of researchers has introduced UCAgent, a novel AI system designed to automate the critical but time-consuming process of functional verification for semiconductor designs. Verification currently consumes about 70% of development time, and traditional methods struggle with modern complexity. UCAgent tackles this by creating a pure Python verification environment using tools like Picker and Toffee, sidestepping the unreliability of having large language models (LLMs) directly generate complex SystemVerilog code. This foundational choice increases the system's robustness.

The agent's power comes from its structured, fine-grained approach. It guides an LLM through a configurable 31-stage verification workflow, where each stage's output is automatically checked for correctness. Furthermore, it employs a Verification Consistency Labeling Mechanism (VCLM) to tag all generated artifacts, ensuring traceability and consistency from specifications to final test cases. In practical experiments, UCAgent successfully completed end-to-end verification on real hardware modules, including UART and floating-point units, achieving exceptional coverage metrics and—most impressively—uncovering design flaws that had been missed by conventional methods.