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trunk/809c385177b92a1666a63a2bf2fdce7b1dbb24e1: Factor out scaled_mm algo checks to non-CUDA (#175657)

PyTorch moves scaled matrix multiplication checks out of CUDA-specific code, enabling future XPU backend integration.

Deep Dive

Meta's PyTorch team has made a strategic code refactor in preparation for expanding hardware support beyond NVIDIA GPUs. In commit 809c385, engineers moved algorithm validation routines for the `_scaled_mm_v2` operation from CUDA-specific implementations into the general `aten::native` layer, maintaining identical functionality while enabling future backend development. This change, part of pull request #175657, represents a crucial architectural shift that decouples algorithmic logic from hardware-specific implementations, allowing the same scaled matrix multiplication operations to run across different accelerator platforms without code duplication.

The technical refactor specifically extracts the `scaled_mm` algorithm checks that were previously embedded within CUDA code, making them accessible to non-CUDA backends like Intel's upcoming XPU architecture. This prepares PyTorch for the multi-vendor hardware landscape where AI workloads increasingly run on diverse accelerators. The change passed existing CUDA tests (`test_scaled_matmul_cuda.py`) and was approved by senior maintainers, indicating robust backward compatibility. For AI developers, this means future PyTorch versions will offer more hardware flexibility for training and inference workloads using scaled matrix multiplication—a fundamental operation in modern transformer models and mixed-precision training.

Key Points
  • Meta engineers refactored PyTorch's scaled matrix multiplication code to move algorithm checks from CUDA to general aten::native layer
  • Change enables future Intel XPU backend support while maintaining full CUDA compatibility through existing test suites
  • Part of broader PyTorch initiative (#170670) to support diverse hardware accelerators beyond NVIDIA GPUs

Why It Matters

Enables PyTorch to run AI workloads on Intel XPUs, reducing NVIDIA dependency and potentially lowering cloud compute costs.