AMD's New AI Chip Gets a Math Fix for Better Accuracy

AMD’s gfx942/MI300 path gets an opt-in round-to-nearest-even preprocessing step for native FP32 GEMMs so MI300 TF32 input conversion tracks NVIDIA TF32 semantics. The path is private and controlled by TORCH_GFX942_ENABLE_RN=1; unset or 0 preserves current behavior.

The article says NVIDIA-to-AMD parity validation found a significant dpa_product_cvr_model NE increase only on MI300 with TF32 enabled, because MI300/gfx942 native XF32 MFMA truncates inputs while NVIDIA Tensor Cores round TF32 inputs to nearest even; MI350, which does not use the same native XF32 path, tracked the NVIDIA baseline with TF32 enabled. The change intercepts mm, addmm, linear, bmm, and baddbmm before AMD GEMM dispatch, requires ROCm, FP32 operands, nonzero alpha, TF32 enabled, TORCH_GFX942_ENABLE_RN=1, and gfx942, and rounds FP32 operands to the TF32 grid while preserving dense layouts and collapsing zero-stride expanded dimensions.

It preserves original operands for hipBLASLt fallback so preprocessing runs only once, covers unset, 0, and 1 control states plus tie-to-even values, signed values, subnormals, finite overflow, infinities, NaNs, expanded batches, and the gfx950 no-op case, and keeps the control internal with no public PyTorch backend API added. Evidence: controlled operator replay covered 44,192 captured rows, including 43,696 computation rows and 15,515 unique signatures, across five deterministic seeds with zero input-fingerprint mismatches; with TF32 enabled, outputs above 1e-3 increased 24.6x and outputs above 1e-2 increased 50.8x; every TF32-only divergence was in the GEMM family, and the MI300 round-to-nearest experiment restored tracking with the comparison baseline. Risk is low while TORCH_GFX942_ENABLE_RN is unset or 0; the enabled path is limited to FP32 native ATen GEMMs with TF32 enabled on gfx942, while MI350, NVIDIA, other dtypes, alpha=0, and TF32-disabled calls retain the existing path.