TREA edge AI chip cuts latency 9x with dual-precision SIMD

TREA, a new edge-AI accelerator from a research team led by Vijay Pratap Sharma, tackles the stringent area-power-latency constraints of edge vision systems. Its core innovation is the DQ-MAC unit, which performs most-significant-digit-first (MSDF) shift-and-add computation with run-time bit truncation, eliminating conventional multiplier overhead and reducing accumulator bit-width. By supporting 4x FxP4 or 1x FxP8 operations per cycle, it achieves up to 4x throughput improvement without hardware duplication. Co-designed with the SIMD datapath, the SHARP pruning strategy enables near 50% structured sparsity while maintaining full MAC utilization. This allows a 3x3 convolution kernel to be computed in 1 cycle in FxP4 mode (vs. 9 cycles in FxP8) and a 5x5 kernel in 3 cycles (vs. 25 cycles), yielding up to 9x latency reduction at the kernel level. The accelerator also integrates a reconfigurable CORDIC-based nonlinear activation function core supporting Sigmoid, Tanh, and ReLU with hardware reuse through time-multiplexing. The full architecture uses a 1D array of 100 SIMD DQ-MAC units with layer-wise hardware reuse, minimizing area and control complexity.

Experimental results demonstrate substantial improvements in latency, hardware utilization, and energy efficiency compared to conventional fixed-precision and non-reconfigurable accelerators. TREA is designed for real-time edge vision workloads like object detection and classification, targeting applications such as autonomous drones, smart cameras, and industrial IoT. By leveraging low-precision computation and structured sparsity, it overcomes the trade-off between accuracy and efficiency. The paper is currently under review at TVLSI and presents a promising direction for deploying deep neural networks on resource-constrained edge devices, potentially enabling high-performance AI inference without relying on cloud connectivity.