MIT Researchers' ATLAS Framework Uses LLM Agents for Reliable Analog Chip Design
New AI system generates functional SAR ADCs that pass rigorous SPICE simulations.
Large Language Models have shown promise in software code generation but struggle with analog electronic design automation (EDA) due to limited circuit topology understanding. Direct prompting leads to hallucinations and schematics that fail SPICE simulations. Researchers from MIT introduce ATLAS, a multi-step agentic framework that overcomes these bottlenecks by grounding LLMs in expert knowledge for planning, selection, parameterization, and iterative modification of analog circuits.
ATLAS incorporates Template-Constrained Generation, which builds toward a generalized SAR ADC generation flow rather than fixed templates. The framework successfully generates functional Successive Approximation Register Analog-to-Digital Converters that pass rigorous simulation validation. As a proof of concept, ATLAS produces SAR ADCs across different technology nodes and input specs, establishing a practical foundation for integrating LLMs into reliable analog design methodologies.
- ATLAS uses multi-step LLM agents grounded in expert knowledge to generate SAR ADCs that pass SPICE simulations.
- Template-Constrained Generation enables a generalized flow across technology nodes, avoiding rigid fixed templates.
- Demonstrated proof-of-concept with successful SAR ADC generation for varying input specs and process nodes.
Why It Matters
Brings reliable LLM assistance to analog chip design, potentially accelerating custom circuit development.