TOPCELL: Topology Optimization of Standard Cell via LLMs

A research team has introduced TOPCELL, a novel framework that applies Large Language Models (LLMs) to the complex, high-dimensional problem of transistor topology optimization in standard cell design. This critical step, which dictates diffusion sharing efficiency and downstream routability, is a persistent bottleneck in advanced semiconductor nodes. Conventional exhaustive search methods become computationally intractable as circuit complexity increases. TOPCELL reformulates this exploration as a generative task, using a fine-tuned LLM to propose optimal layouts that satisfy both the circuit's logical function and the physical constraints of the manufacturing process.

The team employed a specialized training method called Group Relative Policy Optimization (GRPO) to align the model's output with the stringent requirements of industrial chip design. Experimental validation within an industrial flow targeting an advanced 2nm technology node showed that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. Its most striking result came from integration into a state-of-the-art automation flow for a 7nm library generation task. There, TOPCELL exhibited robust zero-shot generalization, matching the layout quality produced by exhaustive solvers while achieving a remarkable 85.91x speedup. This breakthrough, accepted at the prestigious ACM/IEEE Design Automation Conference (DAC 2026), points to a future where AI dramatically accelerates the physical design phase of semiconductor development.