TileSight predicts GPU kernel latency with 12.35% MAPE across architectures

Modern GPU programming frameworks like Triton and TileLang use tiles as first-class primitives, but performance analysis still relies on coarse roofline bounds, black-box ML predictors, or post-hoc profilers. This gap is critical for AI workloads requiring kernel fusion and distributed inference across tensor cores, cache hierarchies, and inter-GPU networks. TileSight elevates the tile from a programming primitive to an analysis primitive, modeling performance from a single core to multi-GPU clusters with a unified tile abstraction.

Inside a GPU core, TileSight models compute-memory pipeline overlap; across cores, it models the cache hierarchy; across GPUs, it models inter-node communication using an alpha-beta cost model. On A100, H200, B200, and B6000, it predicts single-GPU kernel latency with 12.35% pooled mean absolute percentage error (MAPE), outperforming state-of-the-art baselines and transferring well across architectures. Its L2 cache hit rate predictions are within roughly one percentage point of actual measurements. Scaling to 32 GPUs, TileSight achieves 16.18% weighted MAPE on fused distributed kernels and 13.52% wMAPE on end-to-end vLLM serving. In optimization tasks, it selects tile configurations competitive with vendor and expert baselines. The tool will be open-sourced upon publication.