Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging

A research team from the University of Illinois Chicago has published a paper proposing a novel method to solve a critical bottleneck in using LLMs for chip design. Current approaches rely on 'tool-in-the-loop debugging,' where an AI-generated script for an EDA tool is run, fails, and is then repaired based on runtime error feedback. This process is slow, costly, and scales poorly for complex, multi-step design tasks where failures often stem from violated structural dependencies between design objects, not simple syntax errors.

Their solution, a 'verifier-guided synthesis framework,' enforces correctness *before* execution. It represents a design task as a structural dependency graph—an explicit contract of how objects like circuit modules relate. The framework then uses graph-conditioned retrieval, constrained code generation, and staged pre-execution verification to ensure the generated script adheres to this contract. If a potential violation is detected, it performs diagnosis-driven repair without ever calling the actual EDA tool.

The results are substantial efficiency and reliability gains. On single-step tasks, the method achieved an 82.5% pass rate, outperforming both standard LLM+RAG (73.0%) and tool-in-loop debugging (76.0%), while requiring only one tool call per task. The breakthrough is in multi-step workflows: pass rate skyrocketed from a baseline of 30.0% to 70.0%, and further to 84.0% when enhanced with 'trajectory-level reflection.' This decouples correctness from repeated tool interaction, slashing latency and cost.