Spiker-LL FPGA accelerator enables adaptive SNN learning under 0.1 mJ per inference

Deploying adaptive intelligence at the edge has long been hampered by the high computational and energy demands of training neural models. Spiking Neural Networks (SNNs) offer a biologically inspired alternative, but enabling on-device learning requires careful hardware-algorithm co-design. Researchers from the Politecnico di Torino introduce SPIKER-LL, an FPGA-based SNN accelerator that extends the open-source Spiker+ inference architecture. The key innovation is targeted microarchitectural support for the STSF (Spike-Timing Synchrony Feedback) local learning rule, which allows the accelerator to perform both inference and online learning with minimal overhead. Across standard benchmarks like MNIST, F-MNIST, and DIGITS, SPIKER-LL achieves up to 93% accuracy, sub-millisecond latency, and less than 0.1 mJ per inference.

What makes SPIKER-LL particularly compelling for edge deployments is its DSP-free design, which avoids reliance on power-hungry digital signal processing blocks. This makes the accelerator highly scalable for small, low-power FPGAs commonly used in IoT and embedded systems. The results demonstrate that adaptive local learning in SNNs can be realized without sacrificing energy efficiency or speed. SPIKER-LL represents a significant step toward truly intelligent edge devices that can learn and adapt in real time without cloud connectivity. The open-source nature of the project encourages further development and community experimentation, potentially accelerating the adoption of SNNs in applications ranging from sensor processing to autonomous systems.