FPGA-Backed Recursive Clustering Tackles Large TSP with 5-City Clusters
Handles thousands of cities using memory-based FPGA scaling and simulated annealing.
Researchers from the University of Nottingham and related institutions have published a new FPGA-based method for solving Large Traveling Salesman Problems (TSPs) that dramatically improves scalability. Their approach recursively clusters cities into small groups of up to five nodes, each with a centroid. Within each cluster, constrained TSP and simulated annealing are used to derive optimal routes, with neighboring cluster centroids serving as entry and exit points. Inter-cluster connections are then optimized via simulated annealing on the centroids themselves. This hierarchical strategy reduces complexity while preserving solution accuracy.
A key innovation is the hardware implementation on FPGA: the design stores cluster information in memory rather than relying on logic gates, making it independent of FPGA logic resources and scalable based only on available memory. The squared Euclidean distance metric is chosen for distance calculations to minimize resource usage. Compared to prior methods, the proposed system can route many more cities, operates at a higher frequency, and offers better overall scalability. This work represents a significant step toward practical, high-speed TSP solvers for logistics, telecom, and circuit design.
- Recursively partitions cities into clusters of ≤5 nodes with centroid-based routing.
- Uses simulated annealing for both intra-cluster and inter-cluster optimization paths.
- FPGA implementation stores cluster data in memory, enabling scalability independent of logic gates.
Why It Matters
Brings high-frequency, scalable TSP solving to real-world logistics and network optimization tasks.