AI & ESG Framework for Sustainable Semiconductor Manufacturing
A new 6-layer architecture bridges AI process optimization and sustainability compliance.
The semiconductor sector faces a dual challenge: scaling manufacturing with AI while meeting strict sustainability requirements like the EU Carbon Border Adjustment Mechanism (CBAM). In a new scoping review of 1,465 documents from Web of Science and Scopus, researchers Karen Ang and Han-Teng Liao reveal a fragmented “core-periphery” knowledge structure—highlighting a critical gap between AI-driven process optimization and downstream sustainability governance. To bridge this divide, they propose a 6-layer Safe and Sustainable by Design (SSbD) architecture grounded in a System of Systems (SoS) paradigm.
The framework integrates virtual metrology (VM), localized federated learning, and defensive RegTech mechanisms to create provenance-aware data fabrics. It establishes distinct “grid-to-core” and “standards-through-supply-chain” integration pathways, enabling secure, climate-neutral, and circular value chains. The authors argue this positions regulatory compliance as a driver for innovation, not a constraint. The paper is to be presented at the 32nd IEEE ICE/ITMC Conference in Porto, Portugal.
- Review of 1,465 documents reveals a fragmented “core-periphery” knowledge structure in AI, metrology, and ESG.
- Proposed 6-layer SSbD architecture uses virtual metrology, federated learning, and RegTech to bridge AI optimization and sustainability.
- Framework aligns with EU CBAM mandates and aims for secure, climate-neutral, circular semiconductor value chains.
Why It Matters
Provides a blueprint for integrating AI into semiconductor manufacturing without sacrificing sustainability compliance.