SCALE boosts chip design DRV fixes by 25% at sub-2nm nodes

As chip manufacturing pushes toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing becomes increasingly challenging due to complex rule interactions and dense multi-layer routing. While large language models (LLMs) have shown promise in EDA scripting, applying them to visual layout understanding is largely unexplored: diagnosing DRC violations from layout imagery requires precise geometric reasoning and foundry-specific knowledge absent from general-purpose VLMs. The SCALE framework tackles this by serializing multi-layer layout geometry into structured text and fine-tuning a language model to reconstruct randomly masked polygons from surrounding back-end-of-line (BEOL) context alone—without needing any violation labels.

At inference, SCALE uses natural-language rule constraints and high-temperature sampling to steer generation toward diverse, violation-prone layout variants. These variants are validated by an industrial signoff DRC checker, producing annotated layout–violation pairs used to fine-tune a domain-adapted DRC-VLM. This vision-language model then provides rule-aware geometric guidance for local DRV repair. Tested on 100 real sub-2nm cases covering enclosure, spacing, width, and color-spacing violations, SCALE boosts state-of-the-art agents’ solve rates by +12–25%, achieving up to 97% success. This self-supervised approach eliminates the need for expensive labeled data and demonstrates a viable path to automating DRV fixing at advanced nodes.