Graph processor renders 3D Gaussians without DRAM, hints at faster GPU future

Researchers at Imperial College London (Nicholas Fry et al.) have achieved the first-ever implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU) — a graph processor architecture with 1,472 independent tiles, each containing only on-chip SRAM (no DRAM). This closely approximates the constraints of efficient sensor-processor architectures. Input scenes are real-world 3D Gaussian maps. Each tile owns a screen-space region of the framebuffer, and Gaussian primitives are routed to destination tiles via Manhattan-distance hops on a north-east-west-south (NEWS) grid, then distributed to overlapping neighbours in an expanding tree pattern. Computation follows the IPU's Bulk Synchronous Parallel (BSP) model, with inter-tile communication defined at compile time, allowing the hardware to exploit both spatial and temporal locality through local data transfer between cores.

The team evaluated key bottlenecks in this SRAM-only design: inter-tile bandwidth, per-tile SRAM capacity, and workload imbalance caused by non-uniform Gaussian density across scenes. These constraints directly affect performance and render quality. The paper raises broader questions for conventional GPUs and 3D representations, suggesting that direct inter-SM (streaming multiprocessor) communication — analogous to the IPU's inter-tile hops — could offer ways to reduce DRAM access in GPU kernels. This exploration points toward future on-sensor and DRAM-free architectures, potentially enabling ultra-low-power, high-speed 3D rendering for edge devices and augmented reality.