New MRAM-STNO chip combines memory and processing for efficient CNNs
A unified chip achieves 99.76% accuracy on MNIST with 200 pJ per cycle.
A research team led by Ravish Kumar Raj and 11 co-authors from multiple institutions has introduced a novel in-memory computing architecture that unifies magnetic random-access memory (MRAM) synapses with vortex-based spin-torque nano-oscillators (STNO) as neurons. The design targets convolutional neural networks (CNNs) and leverages the non-volatility, high endurance, and CMOS compatibility of MRAM while overcoming traditional limitations like high switching currents and thermal instability. By using 1×8 multistate MRAM arrays coupled to a vortex STNO neuron, the system enables both individual and collective programming of configurable resistance states through fieldline-driven write channels, allowing quantized positive and negative synaptic weights for convolutional and pooling operations.
The architecture was evaluated on several benchmark datasets in simulation, achieving top accuracies of 99.76% on MNIST, 87.93% on SVHN, 78.14% on CIFAR-10, 87.96% on Google Speech Commands, and 56.46% on RadioML. Fabricated device dimensions yield a total chip area of approximately 6171.2 μm², with an average energy consumption of 200.08 pJ per training and inference cycle on MNIST. These results highlight the potential of the unified MRAM-STNO approach for scalable, low-power neuromorphic computing, particularly for edge AI applications where energy efficiency and compact size are critical.
- Unified multistate MRAM synapses and vortex STNO neurons perform in-memory CNN computation on a single chip.
- Achieves 99.76% accuracy on MNIST and 78.14% on CIFAR-10 in simulation.
- Total chip area ~6171 μm² with energy consumption ~200 pJ per cycle, enabling low-power edge AI.
Why It Matters
This MRAM-STNO design could drastically reduce power and area for edge AI inference.