QSimAdv's late-binding architecture beats Aer on NVIDIA and AMD systems
QSimAdv hits 3.4x speedup over Aer at 8 ranks on Setonix
Quantum-circuit simulation just got a portability upgrade that doesn't sacrifice native performance. QSimAdv, a new architecture from a team including Shusen Liu, Pascal Jahan Elahi, and five other researchers, abandons the common-kernel approach to vendor independence. Instead, it uses late binding: representation, operator lowering, and data placement are deferred until inputs become available. This allows the simulator to inspect circuits, noise models, and outputs before full-state allocation, routing eligible sampled-count requests to a stabilizer tableau for speed, while keeping explicit representations fixed.
Benchmarked against Qiskit Aer, QSimAdv leads both Aer Hopper configurations at N=32 on NVIDIA GH200 and Aer's HIP backend on four shared AMD MI250X sizes (N=24–30). On the Setonix supercomputer, QSimAdv dominates every measured rank count, achieving 3.4x and 2.8x speedups over one to eight ranks on GPU and CPU respectively. Weak scaling extends to 256 ranks with 2 TiB GPU and 1 TiB CPU states. The design's first-class logical-to-physical layout map and selective nonlocal target movement keep distributed memory efficient. This proves that portability can live above the kernel boundary while execution remains native—a meaningful advance for quantum research teams locked into specific hardware vendors.
- Late-binding design defers operator lowering and data placement until execution time, enabling vendor-agnostic kernels without sacrificing native performance
- Beats Qiskit Aer at N=32 on GH200 and on four AMD MI250X sizes (N=24–30), with 3.4x GPU speedup on Setonix from 1 to 8 ranks
- Weak scaling reaches 256 ranks with 2 TiB GPU and 1 TiB CPU states, supporting distributed-memory quantum simulation
Why It Matters
QSimAdv removes hardware lock-in for quantum simulation, letting researchers run high-performance workloads on any HPC infrastructure.