Researchers build million-p-bit probabilistic computer for faster optimization
A distributed FPGA network achieves over a trillion flips per second with minimal communication.
A team led by Kerem Camsari (UCSB/Purdue) has realized a programmable probabilistic computer featuring one million p-bits (probabilistic bits) by interconnecting multiple FPGAs into a single distributed Ising machine. Unlike prior p-bit implementations confined to a single chip, this architecture breaks the capacity and memory bandwidth ceiling by keeping all coupling weights in local on-chip memory and exchanging only single-bit boundary states between devices during Gibbs sampling. The system achieves a sampling throughput exceeding one trillion flips per second.
The researchers identified a fundamental tradeoff governed by a single timing ratio, η = f_comm/f_p-bit, where f_comm is the boundary-exchange frequency and f_p-bit is the local update frequency. Above a topology-dependent threshold, the distributed machine matches a monolithic GPU reference; below it, residual energy still decays as a power law but with a reduced exponent. This creates a quantifiable throughput-accuracy tradeoff, modeled theoretically by cluster mean-field theory. Demonstrated on 3D Edwards-Anderson spin glasses, Max-Cut, and SAT problems, the system provides a quantitative design rule for scaling probabilistic computers beyond the single-chip limit.
- Networks FPGAs to create a probabilistic computer with 1,000,000 p-bits, far exceeding single-chip capacity
- Achieves Gibbs sampling at over 1 trillion flips per second while exchanging only 1-bit boundary states between devices
- Introduces a timing ratio η that defines a universal throughput-accuracy tradeoff for distributed stochastic dynamics
Why It Matters
Scales probabilistic computing to industrial-scale optimization and sampling tasks previously impossible on a single chip.