Chapel adds RISC-V support; benchmark study hints HPC future

The Chapel programming language, known for its portable parallel computing model, now officially supports the RISC-V architecture. In this preprint (arXiv:2608.14799), Ian Henriksen and six colleagues from Cray/HPE, Los Alamos National Laboratory, and other institutions describe the changes required to make Chapel work on RISC-V and evaluate the platform's potential for high-performance computing (HPC). The porting process wasn't trivial—they had to address architecture-specific assembly, atomic operations, and runtime assumptions—but the result is a working Chapel toolchain for RISC-V.

To assess readiness, the team ran Chapel's extensive benchmark suite on three RISC-V systems: the SiFive P550, the Unmatched board (based on SiFive's U740), and the Sophon SG2042 (a 64-core RISC-V chip). They compared performance against recent HPC CPUs from x86 and ARM families. While the RISC-V machines are entry-level or developer boards rather than HPC-grade servers, the benchmarks revealed several portability and performance anomalies—some expected, some surprising. Despite the gap in absolute performance, the authors argue the results provide hope that RISC-V hardware can become a viable option for HPC in the near future, especially as the ecosystem around open instruction set architectures continues to grow. The paper is a practical resource for anyone looking to run Chapel or similar parallel languages on RISC-V, and it highlights the software effort needed to make open hardware truly useful for scientific computing.