Coupled inductor arrays achieve 97.4% efficiency for HPC power delivery
250 nH/mm² inductance and 10 A/mm² current density in a package-embedded design
A research team led by Rami Rasheedi, Salma Abdelzaher, and Inna Partin-Vaisband has published a groundbreaking paper on package-embedded coupled inductor arrays for high-performance computing (HPC) power delivery. The proposed framework combines a novel inductor topology with an inductance-island methodology to maximize both inductance and current densities in vertical power delivery (VPD) systems. The topology uses tightly coupled spiral square inductors arranged in arrays, all sharing a common magnetic rod, serving multiple multi-phase converters operating in the same conversion phase. This design is optimized to enhance magnetic coupling while minimizing conversion losses, achieving a remarkable inductance density of 250 nH/mm² and a current density of 10 A/mm². At the system level, the inductance-island methodology partitions the power delivery network into separate islands, each dedicated to a converter phase and supplying a portion of the load current, enabling scalable and efficient power distribution tailored for modern HPC processors.
The framework was validated through extensive simulations. The inductor array was designed and simulated in ANSYS Maxwell 3D and Mechanical, demonstrating an average quality factor of 23.6 and an efficiency of 97.4% at a 2A load current with 6V input at 10 MHz switching frequency. To ensure end-to-end optimization, the inductor netlist was extracted and co-designed in Cadence Virtuoso with a distributed dual-phase power conversion system, jointly optimizing passive and active components. The co-designed converter achieved a significant efficiency gain of 5.65% on average and up to 11.04% at a 40A load compared to a similar converter using uncoupled inductors. This work, accepted for IEEE T-CPMT's special section on vertical power delivery, paves the way for more efficient and scalable power solutions for next-generation advanced packaging and HPC systems.
- Achieves 250 nH/mm² inductance density and 10 A/mm² current density in a package-embedded coupled inductor array.
- Simulated 97.4% efficiency at 2A load current with a quality factor of 23.6 using ANSYS Maxwell 3D.
- Co-designed converter in Cadence Virtuoso shows 5.65% average efficiency gain (up to 11.04% at 40A) over uncoupled inductors.
Why It Matters
Enables scalable, high-efficiency vertical power delivery for next-gen HPC chips and advanced packaging systems.