OpenRTLSet: 131K open-source Verilog samples for LLM hardware design

OpenRTLSet, introduced by Jinghua Wang and colleagues, is the largest fully open-source dataset for hardware design, containing over 131,000 diverse Verilog code samples. The dataset uniquely combines Verilog code from GitHub repositories (102k modules), VHDL translations (5k modules), and synthesizable C/C++ translations (24k modules), all free of proprietary restrictions. Using the reasoning model DeepSeek-R1, the team generated paired natural language descriptions for each sample, enabling fine-tuning of various LLM families such as Qwen and Granite for Verilog code generation. The work explores multiple optimization options, including Verilator-generated C++ files as additional context during labeling, quantization techniques (INT4 vs. BF16), and performance differences across model sizes (7B to 32B parameters).

OpenRTLSet demonstrates that open-source approaches can achieve superior performance in hardware design tasks, establishing a new foundation for accessible research and commercial use in chip design. Accepted at ICLAD'25, the dataset addresses a critical gap in AI-assisted hardware development by providing high-quality, varied training data without licensing barriers. This release is particularly significant for the semiconductor industry, where proprietary datasets have limited progress in generative AI for RTL design. By enabling fine-tuning of models like Qwen and Granite on Verilog code, OpenRTLSet paves the way for more efficient hardware design automation, potentially reducing time-to-market for custom chips.