AMD FPGA accelerates YOLO with 3x power savings via attention approximation

Edge AI object detection demands a delicate balance between accuracy, speed, and power. A new paper from researchers at Hochschule Furtwangen University tackles this by adapting modern attention-based YOLO variants for FPGA deployment. The team (Karki, Ahmed, Jungeblut) introduces a customized Deep Learning Processor Unit (DPU)-aware architecture that makes YOLOv26 and YOLOv11 compatible with AMD Xilinx ZCU104 FPGAs. Their key innovations include replacing unsupported activation functions, substituting split operations with 1x1 convolutions, and approximating spatial attention mechanisms to fit the DPU's constraints. All models were trained and evaluated across six benchmark datasets (COCO, Pascal VOC, KITTI, DOTA, DIOR-R, and an in-house human presence dataset) and tested on all eight DPU configurations (B512 to B4096).

Results show that YOLOv26n delivers the highest end-to-end throughput: 34.05 FPS for standard object detection and 29.55 FPS for oriented (rotated) detection on the ZCU104. Quantization causes an average 5% absolute mAP reduction, but power consumption drops roughly 3x compared to state-of-the-art approaches. The study demonstrates that attention approximation is a viable trade-off for real-time edge inference, enabling efficient deployment of modern YOLO variants on resource-constrained FPGAs without sacrificing too much accuracy. This work is particularly relevant for embedded systems in drones, robotics, and smart cameras where low power and real-time performance are critical.