NeuroRing: Multi-FPGA accelerator runs SNNs faster than real-time

Spiking neural networks (SNNs) promise energy-efficient event-driven computation, but scaling them has been bottlenecked by sparse spike communication and synchronization overhead. Existing CPU, GPU, ASIC, and FPGA solutions each trade off programmability, efficiency, and scalability. To break this trade-off, Muhammad Ihsan Al Hafiz and Artur Podobas present NeuroRing, a modular SNN accelerator built on a stream-dataflow architecture and a bidirectional ring topology. Implemented in High-Level Synthesis (HLS) on FPGAs, NeuroRing supports both single- and multi-FPGA deployments and integrates directly with the NEST simulator, a widely used neuroscience simulation tool. This compatibility means researchers can drop NeuroRing into existing SNN workflows without rewriting code.

Evaluated on the cortical microcircuit benchmark—a standard neuroscience test—NeuroRing achieved a real-time factor (RTF) of 0.83, meaning it simulates 1 second of brain activity in just 0.83 seconds of wall-clock time, faster than real biological time. It also handled a Sudoku constraint-satisfaction workload, demonstrating versatility beyond neuroscience. The system showed meaningful strong and weak scaling across multiple FPGAs and delivered competitive energy efficiency compared to programmable alternatives. Accepted at Euro-Par 2026, NeuroRing positions itself as a flexible, scalable platform for both large-scale brain simulation and broader event-driven applications, potentially accelerating research in neuromorphic computing and low-power AI inference.