Multi-timescale synaptic plasticity on analog neuromorphic hardware

A research team from Heidelberg University has successfully implemented a biologically-inspired, multi-timescale synaptic plasticity rule on the BrainScaleS-2 analog neuromorphic hardware. This breakthrough, detailed in a recent arXiv paper, demonstrates how specialized chips can accelerate the simulation of spiking neural networks—a core model in computational neuroscience. The work specifically maps a calcium-based plasticity rule, central to the synaptic tagging-and-capture hypothesis of long-term memory, onto the chip's hybrid analog-digital architecture. This allows researchers to run simulations of complex learning processes at speeds 1000 times faster than biological real-time, overcoming a major bottleneck in studying long-term neural adaptations.

The implementation cleverly divides the computational labor: the analog circuits of the BrainScaleS-2 chip handle the continuous calcium dynamics, while its embedded digital processors solve the plasticity rule equations numerically. To maintain accuracy despite hardware constraints like integer arithmetic, the team employed techniques like adjustable timesteps and stochastic rounding. The system was validated against a software reference model across four established stimulation protocols, proving its fidelity. This work paves the way for using neuromorphic accelerators not just for AI applications, but as essential tools for hypothesis testing in neuroscience, enabling experiments on learning and memory that would take years to simulate on conventional hardware.