IBM's MorphOPC uses hierarchical learning to boost chip mask optimization
New AI model reduces manufacturing cost while improving printing fidelity on nanoscale chips.
As chip features shrink to nanometer scales, accurately transferring circuit patterns from photomasks to silicon wafers becomes a major challenge. Optical proximity correction (OPC) is used to ensure pattern fidelity, but traditional approaches are computationally expensive. Machine learning surrogate models, particularly encoder-decoder architectures, have emerged as faster alternatives—but they often fail to capture the geometric transformations between target layouts and mask patterns, leading to suboptimal quality.
A team of researchers from IBM (Yuting Hu, Lei Zhuang, Chen Wang, Ruiyang Qin, Hua Xiang, Gi-joon Nam, and Jinjun Xiong) introduces MorphOPC, a multi-scale hierarchical model that reframes mask generation as a sequence of morphological operations on local layout features. By incorporating neural morphological modules, the model learns these geometric transformations end-to-end. On edge-based OPC and inverse lithography technology (ILT) benchmarks across metal and via layers, MorphOPC consistently beats existing state-of-the-art methods, achieving higher printing fidelity and lower manufacturing cost. This work demonstrates strong potential for scalable, AI-driven mask optimization in advanced semiconductor manufacturing.
- MorphOPC outperforms state-of-the-art on both edge-based OPC and ILT benchmarks across metal and via layers.
- Uses a multi-scale hierarchical model with neural morphological modules to learn geometric transformations from target layouts to mask patterns.
- Achieves higher printing fidelity and lower manufacturing cost, enabling scalable mask optimization for nanoscale chips.
Why It Matters
More efficient chip manufacturing with reduced costs and higher yields, critical for next-generation semiconductors.