New technique recovers inference accuracy from memory retention loss in analog AI chips

Analog in-memory computing promises huge energy efficiency gains for AI inference, but a critical challenge has been retention loss—the gradual drift of stored weights that degrades accuracy over time. A new paper from researchers (Brazzini et al.) tackles this head-on using a 65 nm single-poly floating-gate (FG) analog non-volatile memory array fabricated in standard CMOS. They quantify retention loss effects with experimental data and model the impact on neural network accuracy. Without mitigation, accuracy drops significantly after just a few weeks, threatening real-world deployment.

The team combined two complementary approaches: circuit-level compensation and algorithmic batch normalization recalibration. Circuit techniques adjust readout parameters to counteract drift, while the algorithmic step retunes batch normalization layers to adapt to shifted weight distributions. After 60 days since programming, these techniques together recovered baseline inference accuracy to within 2-4% on standard benchmarks (VGG-10 on CIFAR-10 and WideResNet-28-10 on CIFAR-100). This work is a practical step toward making analog AI accelerators viable for long-term field deployment, especially in edge devices where periodic maintenance is impractical.