MiLSD detects line segments under 1MB memory for MCU vision

Line segment detection is critical for visual SLAM, 3D reconstruction, and industrial inspection, but existing deep learning models require several megabytes of memory—far exceeding the capacity of low-cost microcontrollers (MCUs). In a new arXiv preprint, researchers introduce MiLSD (Micro Line-Segment Detector), purpose-built for sub-megabyte memory budgets. The team systematically compared three output representations within a compact fully-convolutional backbone and found that their proposed F-Clip (center-with-length-and-angle) formulation learns most effectively at small model sizes. With 8-bit quantization, MiLSD preserves full-precision performance, while 4-bit quantization causes significant degradation—especially in angle regression—that quantization-aware training only partially recovers.

Operating under a 1MB activation budget, MiLSD improves the ShanghaiTech Wireframe sAP10 metric from 10.6 (using a 25k-parameter, 0.25MB baseline) to 24.1. The full pipeline includes inference enhancements such as sub-pixel decoding, test-time augmentation, and a lightweight verifier. Rather than competing with GPU-scale parsers, the work maps the accuracy-memory trade-off across representations, bit-widths, network capacities, and post-processing strategies for embedded vision systems. This enables advanced computer vision capabilities on cost-constrained devices like drones, robots, and smart cameras.