MCHA architecture smashes MARL workloads with 153x speedup

A team led by Daijing Shi from Peking University has unveiled MCHA (Memory-Centric Hierarchical Architecture), a groundbreaking hardware solution designed to tackle the fundamental limitations of conventional architectures when handling parallel-sequential workloads like Multi-Agent Reinforcement Learning (MARL) and neuromorphic computing.

The architecture introduces a hierarchical communication strategy that distributes data routing across cores, eliminating global buffer saturation and memory bottlenecks. Complemented by a novel parallel-sequential programming model with event-driven triggers, MCHA hides data transmission latency within execution pipelines. Benchmarks show staggering performance gains—performance speedups ranging from 153.06× to 2456.96× over NVIDIA A100 GPUs on MARL workloads—while reducing main memory access from 96% to just 5.44%. The design, synthesized in a 28 nm process, occupies 2.92mm² area and consumes 115.36 mW at 200 MHz, and is fully open-sourced.