Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators

A research team from KAUST, led by Olga Krestinskaya, has published a breakthrough paper on arXiv introducing a novel co-optimization framework for designing next-generation AI hardware. The core problem they address is the current trend of highly specialized in-memory computing (IMC) accelerators, which are custom-built for a single neural network model. This specialization creates inefficiency in real-world deployment where a single chip must run various AI workloads. Their solution is a joint hardware-workload co-optimization method that uses an evolutionary algorithm to find optimal chip architectures that perform well across a diverse set of models, significantly closing the performance gap between specialized and general-purpose designs.

The framework was rigorously tested on both RRAM- and SRAM-based IMC architectures, demonstrating strong robustness. The key metric, the Energy-Delay-Area Product (EDAP), saw dramatic reductions: 76.2% improvement when optimizing for 4 different AI workloads and a staggering 95.5% improvement for a set of 9 workloads. This means future AI accelerator chips could be far more energy-efficient and capable while being smaller, without sacrificing performance across tasks. The team has made the source code publicly available, paving the way for more efficient, general-purpose AI hardware that can power everything from data centers to edge devices without requiring a new chip for every model.