IC3-Evolve: Proof-/Witness-Gated Offline LLM-Driven Heuristic Evolution for IC3 Hardware Model Checking
Researchers automate costly chip verification tuning using offline LLM evolution with proof-gated validation.
A team of researchers has developed IC3-Evolve, a novel framework that automates the notoriously difficult task of tuning heuristic parameters for hardware model checking. The system uses a large language model (LLM) in an offline, evolutionary process to propose small, auditable code patches to an implementation of the IC3 algorithm (also known as Property-Directed Reachability). IC3 is critical for verifying that hardware designs, like CPUs or GPUs, adhere to safety properties, but its performance hinges on a complex web of heuristics that are costly and brittle to tune manually.
The core innovation is a strict 'proof-/witness-gated' validation gate. For a candidate patch to be accepted, any run that concludes a design is SAFE must produce a formal, independently checkable proof (an inductive invariant). Any run that finds a design UNSAFE must produce a concrete, replayable counterexample trace. This gate prevents unsound edits from corrupting the verification tool, ensuring 100% correctness is maintained throughout the automated evolution process.
Because the LLM is used only during the offline evolution phase, the final output is a standard, standalone model checker executable. This evolved verifier has zero ML inference overhead and no runtime dependency on any AI model, making it practical for integration into existing chip design flows. The team demonstrated IC3-Evolve's effectiveness by evolving a checker on the public Hardware Model Checking Competition (HWMCC) benchmark and showing the improvements generalize to unseen public and industrial benchmarks.
- Uses an LLM offline to automatically propose code patches for tuning the heuristic-heavy IC3 verification algorithm.
- Employs a strict 'proof-/witness-gate' where patches are only accepted if they produce verifiable safety proofs or replayable bug traces.
- Produces a standalone, evolved verifier with zero runtime LLM overhead, showing reliable improvements on industrial hardware benchmarks.
Why It Matters
Automates a costly, manual engineering bottleneck in chip design, potentially accelerating verification and reducing time-to-market for complex semiconductors.