IBM's nanostack chip packs 100B transistors, extends Moore's Law

IBM has announced a breakthrough chip prototype that crams approximately 100 billion transistors into an area the size of a fingernail—double the density of its previous state-of-the-art design from 2021. The key innovation is a "nanostack" architecture that vertically stacks transistors in two layers, a departure from traditional planar shrinking that has hit physical limits. Using a complementary field-effect transistor (CFET) approach, IBM builds the chip layer by layer: first fabricating transistors on a silicon layer, then adding a second silicon layer on top with another set of transistors, and finally connecting the two layers electrically. Unlike competing approaches from AMD or Huawei, IBM's design staggers the transistors between layers to simplify wiring and improve alignment precision—critical for performance at these tiny scales.

The new architecture delivers up to 50% more work in the same time and can be 70% more energy efficient than IBM's previous nanosheet-based chips. The transistors themselves use nanosheets just 15 atoms thick, spaced 9 nanometers apart. IBM refers to this technology as "0.7 nanometer" or "sub-nanometer" node. While not yet in production, IBM expects the nanostack to be widely adopted in data centers within a decade, where its power efficiency will help manage soaring energy consumption. IBM will partner with semiconductor manufacturers to produce actual chips, and the design is compatible with both GPUs and CPUs. Industry analysts like Dan Hutcheson of TechInsights call it transformational, adding 10–15 years to the Moore's Law roadmap.