ROS 2 devs explore CPU shared-memory backend for rosidl::Buffer
Could rosidl::Buffer let robots share images and point clouds with zero copies?
Daisuke_Kato, a ROS 2 developer, raised a design question on the ROS General forum about adding a CPU shared-memory backend to rosidl::Buffer, the standard buffer type for serialized message payloads. The motivation is handling large variable-length fields—such as camera images and point clouds—where copying the payload itself dominates overhead. Kato acknowledges that middleware/RMW implementations already offer shared-memory transport and zero-copy optimizations, but asks whether a Buffer-level backend could complement these by making payload storage itself shared, letting a buffer-aware RMW transport a descriptor or reference instead of raw data.
This comes as native buffer support gains momentum: Qualcomm is reportedly working on a buffer implementation that would be the first non-NVIDIA one, referenced in the ROS PMC minutes for July 21, 2026. Kato also points to prior work on CUDA IPC for zero-copy GPU data sharing between ROS 2 processes, and explicitly asks whether sharing backing storage for large payloads is an intended use of the Buffer backend abstraction. The community response has not yet confirmed existing work, making this an open design question with clear implications for robotics performance.
- Developer Daisuke_Kato asks about a CPU shared-memory backend for rosidl::Buffer to avoid copying large payloads
- Qualcomm is building the first non-NVIDIA buffer implementation, hinting at growing vendor interest
- Prior CUDA IPC work shows zero-copy GPU sharing is possible, but CPU shared-memory at the buffer layer remains unexplored
Why It Matters
Zero-copy shared-memory buffers could slash latency and CPU load for robots handling large sensor data in ROS 2.