Researchers deploy AI SAR compression on space-grade FPGAs
New FPGA-based system cuts SAR data volume 10x while running on just 2W...
Deep Dive
Deploying a joint SAR despeckling and compression framework on an embedded ZCU102 FPGA, researchers introduced model adaptations to respect the accelerator's fixed-point arithmetic and limited operations. Testing across CPU, GPU, and FPGA, they found that replacing GDN activations with ReLU improves quality on SAR, residual blocks add little benefit for ten times the compute, and the FPGA is the most energy-efficient platform tested—offering a functional edge deployment workflow for onboard SAR compression.
Key Points
- Deployed joint SAR compression and despeckling on Xilinx ZCU102 FPGA with 2W power consumption
- Model adaptations included ReLU activation replacement and residual block removal for efficiency
- FPGA implementation proved 10x more energy-efficient than GPU/CPU baselines while achieving better compression
Why It Matters
Enables near-real-time Earth observation by reducing SAR downlink bottlenecks while operating within space mission power constraints