Graph-Based ECO and Patch Generation for High-Level Synthesis
New AI methodology automates late-stage chip design changes, preserving schedules and ensuring zero errors.
A team from Google and the University of New Brunswick has published a research paper introducing a novel, automated system for handling Engineering Change Orders (ECOs) in chip design. The methodology is specifically built for Google's open-source High-Level Synthesis (HLS) toolchain, XLS. It tackles a major pain point: current HLS tools offer limited support for late-stage design modifications, forcing engineers into manual, error-prone, and expensive rework cycles whenever a specification changes after significant development.
The core innovation is a graph-based patch generation system. It employs a Graph Edit Distance (GED) algorithm to automatically detect structural differences between the original and revised versions of a design's Intermediate Representation (IR). The system then transforms these differences into a sequence of patch operations. Crucially, it includes a patch application mechanism that enforces the XLS IR's constraints to maintain semantic correctness and a schedule constraining scheme that preserves the original pipeline registers, preventing performance regression.
Experiments conducted across several XLS designs demonstrated the approach's effectiveness. The system achieved high structural reuse ratios, successfully preserved the original scheduling, and—most importantly—maintained full functional correctness in all tested cases. This proves the methodology is not just theoretical but practical for integration into production HLS workflows, where reliability is paramount.
- Automates ECOs for Google's XLS HLS tool using a Graph Edit Distance (GED) algorithm to detect design differences.
- Generates and applies patches that enforce IR constraints and preserve original pipeline schedules, preventing performance loss.
- Validated on multiple designs, achieving high structural reuse and 100% functional correctness, enabling practical production use.
Why It Matters
Dramatically reduces the time, cost, and risk of making late-stage changes to complex silicon designs, accelerating hardware development cycles.