DeepSig's CUDA acceleration speeds 5G PHY up to 91x on DGX Spark

DeepSig, known for RF machine learning, released an arXiv paper describing a CUDA acceleration backend for its OCUDU 5G physical layer and O-RAN fronthaul path. The implementation accelerates PDSCH, PUSCH, SRS, PRACH, split-8 lower-PHY transforms, and O-FH IQ compression/decompression without requiring changes to existing factories, resource-grid interfaces, PRACH-buffer interfaces, or channel processors. It uses CUDA-visible grids, device-side softbit buffers, stream events, pinned staging buffers, and managed-memory policies to keep data resident on the accelerator, minimizing PCIe transfers. The team benchmarked the design on an NVIDIA DGX Spark with a GB10 GPU and ARM CPU host, comparing against production CPU baselines pinned to high-capacity cores.

Representative measurements show substantial speedups: 10.3x for PUSCH, 2.7x for PDSCH, 19.7x for split-8 low-PHY RX with slot-shaped batching and scattered mapped zero-copy, 91.4x for O-FH BFP12 decompression, and 28.8x for PRACH detection. Crucially, the 10% BLER thresholds for CPU and GPU agreed within 0.064 dB in tested PUSCH sweeps, indicating the accelerated path preserves link performance. Beyond raw throughput, the GPU-resident pipeline doubles as an execution substrate for AI-RAN, enabling machine-learned channel estimation, neural receivers, and AI-native air-interface research to run beside standards-compliant baseband kernels. This positions DeepSig's approach as a practical foundation for software-defined 5G and O-RAN platforms that leverage general-purpose AI hardware.