GoGoTB achieves 98.4% line coverage in agentic RTL verification
Automated chip verification hits 100% environment generation success without human help...
Functional verification consumes a huge chunk of IC front-end engineering, and a single undetected bug can trigger a costly silicon respin. Large language models (LLMs) have been applied to automate parts of this process, but existing approaches generate testbench components via isolated single-turn calls—no shared context, so interface mismatches slip through and coverage reporting stays decoupled from specification requirements. That leaves verification gaps that are hard to diagnose or fix.
GoGoTB tackles this with three integrated subsystems: an agentic execution control layer that separates deterministic enforcement from LLM reasoning at every tool boundary, an evolvable knowledge system that dispatches methodology and design-specific expertise on demand, and a specification-grounded coverage closure framework that anchors every coverage bin to a named specification behavior. Tested on 8 RTL designs without any human intervention, GoGoTB achieves 100% environment generation success and averages 98.4% line, 97.2% branch, 97.0% toggle, and 83.2% functional coverage. No prior work could generate a complete verification environment or reach meaningful coverage on the same benchmarks.
- GoGoTB achieves 100% environment generation success across 8 RTL designs with zero human intervention.
- Average coverage: 98.4% line, 97.2% branch, 97.0% toggle, and 83.2% functional coverage—significantly outperforming prior LLM-based approaches.
- Three subsystems—agentic execution control, evolvable knowledge system, and specification-grounded coverage closure—enable end-to-end verification closure with diagnosable root causes for residual gaps.
Why It Matters
Agentic AI closes the verification gap, slashing respin costs and accelerating chip design cycles.