New paper automates PID tuning for time-delay plants with certified controllers

Senol Gulgonul (independent researcher) has published a paper on arXiv that closes a critical gap in the unified PID/PI analysis for time-delay plants recently introduced by An et al. (Automatica, 2026). That prior work combined the D-partition method with a boundary gradient vector (BGV) to map stabilizing, relative-stability, and stability-margin regions, but left two manual steps: an interior-point test to determine unstable-pole counts in each cell, and a user-driven choice of a single controller from the admissible region. Gulgonul's first contribution provides analytic formulas for the absolute unstable-pole count—using companion-matrix or Routh counts for delay-free designs and argument-principle (Mikhailov) evaluations for retarded delay loops—thus fully automating cell labeling and eliminating the interior-point test. His second contribution adds a time-domain selection rule that returns one certified controller: among monotone step responses, he chooses the minimum-settling-time PI gains, whose tangency condition is derived, with monotonicity guaranteed by external positivity (a nonnegative closed-loop impulse response).

Gulgonul's third contribution flags a neutral-type pitfall that the unified analysis never delimits: an ideal PID with derivative action on a first-order-plus-dead-time (FOPTD) plant becomes neutral type, with a root chain on the imaginary axis when kKd = T. He reproduces the authors' delay-free benchmark exactly, recovering both admissible Kp intervals, and demonstrates the full pipeline on a FOPTD plant, delivering a certified monotone, fast-settling PI controller that the region-only method can neither locate nor justify. The selected gains match an independent closed-form tangency rule to within 1%. All claims are validated numerically. This work effectively transforms the previous feasibility framework into a complete, automated design tool for industrial practitioners working with time-delay systems.