FlexRC speeds up many-port RC circuit simulation with flexible reduction
New method cuts simulation time by generating sparse reduced models with user-controlled accuracy.
Efficient simulation of post-layout resistor-capacitor (RC) networks with many ports is critical for chip design verification. Traditional elimination-based reduction methods suffer from fixed frequency points, overly large reduced models, or high computational cost. In a new arXiv paper, Yuncheng Xu and six co-authors introduce FlexRC, a flexible multi-point model order reduction technique designed specifically for many-port RC networks.
FlexRC starts with the same elimination step as prior work but diverges by constructing a nonorthogonal projection basis via a modified block rational Arnoldi process, resulting in a sparse banded reduced model. Users can specify frequency points of interest, apply a tolerance-controlled port-reduction to the internal subsystem, and optionally enable sparsity control to further reduce model complexity. The authors analyze passivity under port-reduction perturbations, prove moment matching, and provide conservative error estimates. Numerical experiments on industrial RC examples and IBM power-grid benchmarks demonstrate FlexRC's effectiveness in both reduction time and transient simulation time, offering a practical solution for large-scale circuit analysis.
- FlexRC uses a modified block rational Arnoldi process to generate sparse banded reduced models.
- Three adjustable components: user-specified frequency points, tolerance-controlled port-reduction, and optional sparsity control.
- Tested on industrial RC and IBM power-grid examples; shows faster reduction and transient simulation than existing methods.
Why It Matters
Faster, more flexible circuit simulation for chip designers, enabling quicker verification of complex power-grid and interconnect networks.