Extension of ACETONE C code generator for multi-core architectures

A team of researchers from IRIT-TRACES, including Yanis Aït-Aïssa and Claire Pagetti, has initiated a major extension of the ACETONE framework. ACETONE is a specialized tool that generates predictable, verifiable C code from machine learning models for use in safety-critical embedded systems, such as those in aircraft or cars. Its current limitation is that it only produces sequential code, which fails to utilize the parallel processing power of modern multi-core chips common in these industries. The team's paper, submitted to the 2026 ERTS conference, lays the formal groundwork for this upgrade by defining the core processor assignment problem and surveying existing parallelization solutions.

The planned extension involves three key technical components: implementing a scheduling heuristic to assign computational tasks to different processor cores, creating code templates that handle the necessary synchronization between these parallel tasks, and conducting a formal evaluation of the worst-case execution time (WCET) for the new framework's layers. Successfully adding parallel code generation would be a significant leap, allowing complex AI models to run faster and more efficiently on the hardware they are deployed on, without sacrificing the deterministic behavior required for certification in fields like aerospace and automotive. This work bridges a crucial gap between advanced machine learning and the stringent reliability needs of real-time, safety-critical computing.