EULER-ADAS chip cuts power 71.9% for real-time self-driving AI inference

EULER-ADAS introduces a SIMD-enabled bounded-regime Posit representation that combines stage-adaptive logarithmic mantissa multiplication with bit truncation and a shared quire accumulation path. This unified architecture supports Posit-(8,0), Posit-(16,1), and Posit-(32,2) execution modes without duplicating precision-specific hardware, allowing 4x Posit-8, 2x Posit-16, or 1x Posit-32 operations from the same datapath.

On FPGA, the bounded variants reduce LUT count by up to 41.4%, delay by up to 76.1%, and power by up to 71.9% compared to exact Posit engines. In 28-nm CMOS, the EULER-ADAS core occupies just 0.013–0.016 mm², consumes 19.8–22.1 mW, and clocks at up to 1.84 GHz. Application benchmarks across image classification, ADAS, and edge workloads show Posit-16 and Posit-32 remain within ~1.5 percentage points of FP32 accuracy.

A full TinyYOLOv3 prototype on the Xilinx Pynq-Z2 board achieves 78 ms per frame at 0.29 W (22.6 mJ/frame), demonstrating suitability for power-constrained, real-time ADAS inference. The design also achieves up to 10× lower energy-delay product than conventional radix-4 Booth-based Posit multipliers.

By combining precision reconfigurability with logarithmic arithmetic, EULER-ADAS provides a practical path for deploying neural networks in automotive and edge environments where power budgets are tight but accuracy demands remain high.