UChicago researcher builds FLOP verification system for AI treaty compliance
Using side-channel GPU readings to verify training compute without exposing model secrets.
Deep Dive
William Fowler from UChicago's Existential Risks Lab built a minimum viable product to verify LLM training FLOPs using side-channel GPU readings on an Nvidia Jetson Orin Nano. The system monitors power (via an INA3221 sensor) and memory bandwidth utilization (via Actmon) to estimate training compute without accessing code or data. This addresses AI policy needs for verifying compute thresholds like 10^26 FLOPs in California's SB 53 and 10^25 in the EU AI Act.
Key Points
- UChicago researcher uses power (INA3221) and memory bandwidth (Actmon) side-channels on Nvidia Jetson Orin Nano to estimate training FLOPs
- Method addresses AI treaty verification needs, targeting compute thresholds like 10^26 FLOPs (SB 53) and 10^25 FLOPs (EU AI Act)
- MVP mimics transformer training on a single-board computer, proving concept for non-invasive on-site verification without exposing code or data
Why It Matters
Enables verifiable AI compute thresholds for international treaties, reducing reliance on self-reported data from AI companies.