E-ReCON chip achieves 419 TOPS/W for edge AI inference

Researchers from the Indian Institute of Technology Indore have unveiled E-ReCON, a 16Kb digital compute-in-memory (DCIM) macro built on a compact 3T1R ReRAM bitcell that occupies just 0.85 µm². Designed for edge-AI inference, the macro supports reliable AND-based in-memory multiplication for both conventional convolutional neural networks (CNNs) and spiking neural networks (SNNs). A key innovation is an interleaved 10T/28T adder tree that reduces transistor count by 37% and power consumption by 28% compared to conventional 28T RCA-based designs. Fabricated in 65nm CMOS at 1.2V, E-ReCON achieves a minimum latency of 0.48ns, throughput ranging from 2.31 to 3.1 TOPS, and peak energy efficiency of 419 TOPS/W.

Evaluated on LeNet-5, AlexNet, and CNN-8 models, the macro delivered 97.81%, 93.23%, and 96.51% accuracy on MNIST/A-Z, CIFAR10, and SVHN datasets respectively. With 40% pruning, it retained nearly 99.8% of original accuracy while reducing MAC operations and computation cycles. For SNN workloads, the AND-type bitcell efficiently handles spike-weight multiplication with low switching activity; a 2A2W configuration achieved accuracy close to FP32 baselines on VGG-8, VGG-16, and ResNet-18 across CIFAR-10, CIFAR-100, and ImageNet-1K. Compared to prior ADC-based ReRAM-CIM designs, the architecture improves latency and energy efficiency by 30-40% while maintaining robustness under full PVT and ReRAM variability, making it a scalable platform for next-generation edge-AI, IoT, biomedical sensing, and neuromorphic applications.