TinyGAN gets 12.6M-parameter DCGAN running on $2 RISC-V MCU
Pure C inference generates 64x64 cat faces in 26 seconds on 512KB SRAM.
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A developer known as Separate-Choice has demonstrated that generative adversarial networks (GANs) can run on ultra-low-cost microcontrollers—specifically, the dual-core RISC-V CH32H417 MCU. Their TinyGAN project uses a pure C inference engine (no TFLite, no CMSIS NN) to generate 64x64 pixel cat faces from a 12.6M-parameter DCGAN. The model is quantized to int8 per channel, and intermediate activations use the chip’s 512KB of DTCM SRAM. Layer weights are streamed from an SD card using double buffering: the next layer loads while the current one computes. The SD card access speed is the bottleneck—not computation—yielding a 26-second generation time.
The project also incorporates a quantum twist: the latent vector is seeded from 200 bytes of quantum random data sourced from ANU QRNG (vacuum fluctuation). A single quantum bit then classifies the generated cat as “motivated” or “demotivated,” selecting from a phrase bank of four fragment slots, enabling 131,072 possible spoken verdicts output via the onboard DAC. This blend of low-cost MCU inference, pure C implementation, and quantum entropy sampling makes TinyGAN a unique proof-of-concept for AI at the edge without ARM’s ecosystem.
- Pure C inference engine for 12.6M-parameter DCGAN on a RISC-V MCU (CH32H417) with no TFLite or CMSIS NN.
- Double buffering streams layer weights from SD card, overcoming 512KB SRAM constraint; bottleneck is SD card speed.
- Latent vector seeded by 200 bytes of quantum random data (ANU QRNG), with a single quantum bit classifying the generated image.
Why It Matters
Proves GAN inference is viable on sub-$5 RISC-V MCUs, expanding edge AI beyond ARM’s ecosystem.