New Wiring Makes AI Chips Talk 80% Faster and Cheaper

Here's the problem nobody talks about. A modern AI model is far too big to live on a single chip, so it gets chopped up and spread across dozens or hundreds of chips inside a data center. That means the real bottleneck isn't the chips themselves — it's the conversation between them. Today's setups connect chips using the same kind of networking as the internet, called RoCE (a way of sending data over standard Ethernet cables). It works, but it's like mailing letters between offices instead of just shouting down a hallway: slower, more expensive, more power-hungry.

A team of researchers has now published a design called Co-Fabric that replaces that letter-mailing with a shared hallway. Instead of treating each chip as a separate address on a network, it gives every chip one unified address across the whole system — the technical trick that makes the speed-up possible. Testing on a 64-chip setup arranged in a 3D grid, the team reports communication delays cut by more than half and data flow improved 2 to 5 times compared with RoCE. When they ran DeepSeek R1, a popular open AI model, it answered 30% to 80% faster.

The money angle is just as interesting. Because Co-Fabric uses a simpler four-layer protocol (think fewer forms to fill out for every message), the hardware connecting the chips costs up to 80% less and draws about 5% less power. AI companies spend enormous sums on these connections, and that cost eventually shows up in what you pay for AI tools — or in whether they're profitable at all. Cheaper, more efficient wiring is one of the few levers that lowers AI prices without making the AI itself worse.

The catch: this is a research paper, not a product you can buy. The results come from one specific 64-chip test system, and the 80% saving applies only to the interconnect hardware, not to a whole data center. Chip and server makers would need to redesign their hardware around it. Useful, promising — but not yet shipping.