PyTorch XPU patch skips CUDA stream code for SYCL in-order queues
PyTorch XPU update drops CUDA stream events—SYCL queues handle it natively
A new PyTorch pull request (ciflow/xpu/190637) by contributor xuhancn targets a long-standing compatibility issue in the AOTI (Ahead-of-Time Inductor) C++ wrapper for XPU devices. The change removes CUDA-specific stream event code generation from four paths in CppWrapperGpu. These paths were originally added by PR #182971 to support user streams, emitting helper classes like AOTIPerThreadEventCache and AOTIPerThreadStreamCache along with cudaEventRecord/cudaEventSynchronize calls. However, XPU devices running SYCL use in-order queues that implicitly handle event ordering, making these CUDA constructs unnecessary and potentially causing runtime failures.
The four skipped paths are: codegen_stream_info_prologue(), triggered when multiple streams are detected; _emit_stream_op_inline(), used for stream operations like record_event; and codegen_enter_cuda_stream_context()/codegen_exit_cuda_stream_context(), invoked when switching to non-default streams. By bypassing them, PyTorch's XPU backend relies on SYCL's native implicit ordering instead of forcing CUDA-style synchronization. The fix was verified on Intel's Ponte Vecchio (PVC, driver 1.6.33578) and Battlemage (BMG, Intel Arc Pro B60), with D2H (device-to-host) copies passing. This directly resolves GitHub issues #189327 and #189326, marking a cleaner, non-CUDA-dependent path for Intel GPU users in PyTorch.
- Skips 4 CUDA-specific codegen paths in CppWrapperGpu for XPU: stream info prologue, inline stream ops, and enter/exit CUDA stream context.
- Leverages SYCL in-order queue semantics—no explicit event recording needed on Intel GPUs.
- Verified on Intel PVC (driver 1.6.33578) and BMG (Arc Pro B60); D2H copy passes and fixes issues #189327 and #189326.
Why It Matters
This streamlines PyTorch XPU AOTI compilation, removing CUDA dependencies and enabling reliable D2H copies on Intel GPUs.