Researchers unveil C2C-Explorer to supercharge LLM cloud chips
New framework cuts LLM chip interconnect simulation time by 7.8x and boosts performance by 44%.
A 13-member research team led by Jiayi Li has released C2C-Explorer, an open-source framework designed to tackle the interconnect bottlenecks in multi-chip LLM cloud systems. The tool integrates three core components: a workload-driven traffic generator that produces realistic C2C communication patterns for LLM workloads, a scalable interconnect simulator capable of modeling up to 512 chips using hybrid cycle/event modeling, and a metric-guided evaluator that enables systematic architecture co-design.
When tested against FPGA-based C2C prototypes, the simulator achieved 2.46-8.23% end-to-end timing error across diverse traffic patterns while accelerating large-scale simulations by up to 7.8x compared to cycle-accurate baselines. In a practical deployment scenario with a 32-XPU system running DeepSeek-R1-671B inference, C2C-Explorer identified configurations that improved goodput by 44.1% and reduced memory usage by 98.4%. The framework is now available on arXiv and targets DAC'26 acceptance.
- C2C-Explorer combines LLM traffic generation, scalable simulation (up to 512 chips), and Bayesian design space exploration into a unified pipeline
- Validated against FPGA prototypes with 2.46-8.23% timing accuracy and 7.8x faster simulation via hybrid cycle/event modeling
- Boosts goodput by 44.1% and cuts memory usage by 98.4% in 32-XPU DeepSeek-R1-671B inference workloads
Why It Matters
Cuts LLM cloud deployment costs while unlocking 2x performance gains through smarter chip interconnects