BitFair: New 12nm chip cuts XR neural net energy by 22x with smart bit skipping

Researchers Ang Li and Chang Gao have introduced BitFair, a software-hardware co-designed bit-serial CNN accelerator tailored for ultra-low-power extended reality (XR) wearables. Fabricated in GlobalFoundries 12nm FinFET, the chip occupies only 0.34mm² of core area and includes 104KB of on-chip memory. It operates at voltages between 0.55V and 0.70V, enabling sub-millisecond inference latency while delivering up to 117.0 billion ternary operations per watt (BTOPS/W) and 0.07 picojoules per signed operation (pJ/SOP). The key innovation is a learnable early termination mechanism that exploits dynamic bit-level sparsity: per-layer thresholds are trained to predict when the final ReLU output will be zero, at which point the remaining bit computations are skipped entirely. Additionally, an adaptive bit ordering searches for layer-wise sequences that prioritize the most informative bits, maximizing early termination without degrading model accuracy.

BitFair was evaluated on two neuromorphic datasets: IBM DVS128 Gesture and N-MNIST, achieving 96.5% and 97.7% accuracy respectively. Compared to prior fabricated XR vision accelerators, BitFair improves effective energy efficiency by 4.0x to 22.1x and boosts accuracy by up to 9.2%. These results demonstrate that bit-level sparsity exploitation combined with learnable decision boundaries can dramatically reduce the power consumption of always-on XR perception systems. The paper is currently under review and available on arXiv (2607.05445).