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llama.cpp b9519 brings CUDA-level MMVQ optimization to SYCL backends

Multi-column mat-vec now runs up to 2x faster on Intel and other SYCL devices.

Deep Dive

ggml-org’s llama.cpp has shipped b9519, a release that ports the multi-column MMVQ (matrix-vector quantized multiply) kernel from the CUDA backend to SYCL. This enables SYCL-enabled hardware—such as Intel GPUs, AMD GPUs via oneAPI, and other conformant accelerators—to benefit from an optimization that was previously exclusive to NVIDIA hardware. The key change: weights are now read once per dispatch instead of once per column, significantly reducing memory bandwidth pressure. The optimization covers all standard quant types (Q4_0, Q8_0, Q3_K, Q4_K, Q5_K, Q6_K) and reorder paths for Q4_0 and Q8_0. IQ types (except IQ4_XS) are omitted due to incompatible vec_dot signatures.

Beyond the core SYCL port, the fix addresses a critical performance regression for multi-token scenarios. Previously, the weight reorder kernel was only bootstrapped on single-token mat-vec (ne[1] == 1). This meant that speculative decoding and multi-token prediction (MTP) verify operations—which use multi-column mat-vec—never triggered the reorder, forcing them to run on the slower non-reorder kernel. With b9519, the bootstrap is extended to small multi-column batches (ne[1] ≤ 8), delivering measurable speedups for real-world LLM inference pipelines that rely on batched token generation.

Key Points
  • Multi-column MMVQ kernel ported from CUDA to SYCL, covering Q4_0, Q8_0, Q3_K, Q4_K, Q5_K, Q6_K quant types.
  • Weights read once per dispatch instead of per column, reducing memory bandwidth by up to 50%.
  • Weight reorder now bootstraps on batches up to ne[1] ≤ 8, fixing a bottleneck in speculative decoding and MTP verify.

Why It Matters

Professionals running LLMs on Intel or AMD GPUs via SYCL get near-CUDA-level inference speed, especially during batched token generation.

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