An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices

A team of researchers has published a breakthrough paper detailing an ultra-low-power, synthesizable encoder chip designed for the next generation of neuromorphic edge devices. The core innovation is an asynchronous, tree-based Address-Event Representation (AER) encoder that can be built using standard commercial Electronic Design Automation (EDA) toolkits from Cadence. This approach replaces specialized analog components with a digital design that uses edge-triggered flip-flops and a novel random-priority arbiter, making it compatible with mainstream chip manufacturing flows. The result is a scalable architecture that can efficiently translate sparse, event-driven sensor data (like from neuromorphic cameras) into a digital format for processing.

An 8-event prototype was fabricated using a 65nm CMOS process, and post-silicon measurements confirm its exceptional performance. The chip demonstrates a peak throughput of 33 million events per second with an average latency of just 50 nanoseconds. Most impressively, it achieves this speed while consuming a minuscule 435 femtojoules (fJ) of energy per encoded event. This combination of high speed and ultra-low power is critical for deploying always-on, intelligent sensing in battery-constrained edge devices, from smart sensors to autonomous drones, where processing efficiency is paramount.